1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a multi-time programmable (MTP) memory and a method of manufacturing the same for superior data retention.
2. Description of Related Art
A multi-time programmable (MTP) memory device is a type of a memory device that allows multiple data writing, reading and erasing operations, and the data stored in the MTP memory can be retained even after power supply to the device is cut off. With the aforesaid advantages, the MTP memory has been widely employed in personal computers and electronic equipment.
Typically, a floating gate and a control gate of the MTP memory device are generally fabricated using doped polysilicon. The floating gate is sandwiched between the control gate and a substrate and is disposed in a floating state without connecting to other circuits, while the control gate is connected to a word line. In addition, the MTP memory also includes a tunneling oxide layer disposed between the substrate and the floating gate and an inter-gate dielectric layer disposed between the floating gate and the control gate.
The most common issue of the MTP memory device is related to undesirable data retention. One of the major factors resulting in insufficient data retention lies in the inter-gate dielectric layer disposed between the control gate and the floating gate. In other words, the data retention of the MTP memory device is determined by the quality of the inter-gate dielectric layer between the control gate and the floating gate.
A method of fabricating a conventional MTP memory device includes the following steps. First, a polysilicon layer and a mask layer are formed and patterned. The patterned polysilicon layer is utilized as a floating gate. Next, a growth process is performed to form a gate oxide layer of a high voltage device. Thereafter, the mask layer is removed, and growth processes are then performed to sequentially construct a gate oxide layer of a medium voltage device and a gate oxide layer of a low voltage device, respectively. Besides, a silicon oxide layer is formed on top of the floating gate as an inter-gate dielectric layer. Afterwards, a control gate is constructed. According to the aforesaid manufacturing process, the inter-gate dielectric layer disposed on top of the floating gate is formed during the growth processes of the gate oxide layer of the medium voltage device and the low voltage device. Thus, a thickness of the inter-gate dielectric layer is usually less than 150 angstroms, which leads to defects in the inter-gate dielectric layer. With said defects existing in the inter-gate dielectric layer between the control gate and the floating gate, electrical charges stored in the floating gate enter the control gate through said defects, easily causing leakage current of the device. In addition, the inter-gate dielectric layer between a top corner of the floating gate and the control gate is in a relatively thin thickness, and leakage current of the device is generated more easily, deteriorating reliability of the device.